;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name          : startup_stm32f10x_hd.s
;* Author             : MCD Application Team
;* Version            : V3.5.0
;* Date               : 11-March-2011
;* Description        : STM32F10x High Density Devices vector table for MDK-ARM 
;*                      toolchain. 
;*                      This module performs:
;*                      - Set the initial SP
;*                      - Set the initial PC == Reset_Handler
;*                      - Set the vector table entries with the exceptions ISR address
;*                      - Configure the clock system and also configure the external 
;*                        SRAM mounted on STM3210E-EVAL board to be used as data 
;*                        memory (optional, to be enabled by user)
;*                      - Branches to __main in the C library (which eventually
;*                        calls main()).
;*                      After Reset the CortexM3 processor is in Thread mode,
;*                      priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>   
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************

; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Stack_Size      EQU     0x00000400

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size
__initial_sp
                                                  
; <h> Heap Configuration
;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Heap_Size       EQU     0x00000000

                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem        SPACE   Heap_Size
__heap_limit

                PRESERVE8
                THUMB
;******************************************************************************
;                                  IMPORTS
;******************************************************************************
				
				IMPORT  stm32f103x_app_int_handler_NMI
				IMPORT  stm32f103x_app_int_handler_HardFault
				IMPORT  stm32f103x_app_int_handler_MemManage
				IMPORT  stm32f103x_app_int_handler_BusFault
				IMPORT  stm32f103x_app_int_handler_UsageFault
				IMPORT  stm32f103x_app_int_handler_SVC
				IMPORT  stm32f103x_app_int_handler_DebugMon
		        IMPORT	OS_CPU_SysTickHandler
		        IMPORT	OS_CPU_PendSVHandler
				
		        IMPORT	stm32f103x_bsp_int_handler_WWDG
		        IMPORT	stm32f103x_bsp_int_handler_PVD
		        IMPORT	stm32f103x_bsp_int_handler_TAMPER
		        IMPORT	stm32f103x_bsp_int_handler_RTC
		        IMPORT	stm32f103x_bsp_int_handler_FLASH
		        IMPORT	stm32f103x_bsp_int_handler_RCC
		        IMPORT	stm32f103x_bsp_int_handler_EXTI0
		        IMPORT	stm32f103x_bsp_int_handler_EXTI1
		        IMPORT	stm32f103x_bsp_int_handler_EXTI2
		        IMPORT	stm32f103x_bsp_int_handler_EXTI3
		        IMPORT	stm32f103x_bsp_int_handler_EXTI4
		        IMPORT	stm32f103x_bsp_int_handler_DMA1_CH1
		        IMPORT	stm32f103x_bsp_int_handler_DMA1_CH2
		        IMPORT	stm32f103x_bsp_int_handler_DMA1_CH3
		        IMPORT	stm32f103x_bsp_int_handler_DMA1_CH4
		        IMPORT	stm32f103x_bsp_int_handler_DMA1_CH5

		        IMPORT	stm32f103x_bsp_int_handler_DMA1_CH6
		        IMPORT	stm32f103x_bsp_int_handler_DMA1_CH7
		        IMPORT	stm32f103x_bsp_int_handler_ADC1_2
		        IMPORT	stm32f103x_bsp_int_handler_USB_HP_CAN_TX
		        IMPORT	stm32f103x_bsp_int_handler_USB_LP_CAN_RX0
		        IMPORT	stm32f103x_bsp_int_handler_CAN_RX1
		        IMPORT	stm32f103x_bsp_int_handler_CAN_SCE
		        IMPORT	stm32f103x_bsp_int_handler_EXTI9_5
		        IMPORT	stm32f103x_bsp_int_handler_TIM1_BRK
		        IMPORT	stm32f103x_bsp_int_handler_TIM1_UP
		        IMPORT	stm32f103x_bsp_int_handler_TIM1_TRG_COM
		        IMPORT	stm32f103x_bsp_int_handler_TIM1_CC
		        IMPORT	stm32f103x_bsp_int_handler_TIM2
		        IMPORT	stm32f103x_bsp_int_handler_TIM3
		        IMPORT	stm32f103x_bsp_int_handler_TIM4
		        IMPORT	stm32f103x_bsp_int_handler_I2C1_EV

		        IMPORT	stm32f103x_bsp_int_handler_I2C1_ER
		        IMPORT	stm32f103x_bsp_int_handler_I2C2_EV
		        IMPORT	stm32f103x_bsp_int_handler_I2C2_ER
		        IMPORT	stm32f103x_bsp_int_handler_SPI1
		        IMPORT	stm32f103x_bsp_int_handler_SPI2
		        IMPORT	stm32f103x_bsp_int_handler_USART1
		        IMPORT	stm32f103x_bsp_int_handler_USART2
		        IMPORT	stm32f103x_bsp_int_handler_USART3 
		        IMPORT	stm32f103x_bsp_int_handler_EXTI15_10
		        IMPORT	stm32f103x_bsp_int_handler_RTCAlarm
		        IMPORT	stm32f103x_bsp_int_handler_USBWakeUp
				IMPORT  stm32f103x_bsp_int_handler_TIM8_BRK
				IMPORT  stm32f103x_bsp_int_handler_TIM8_UP
				IMPORT  stm32f103x_bsp_int_handler_TIM8_TRG_COM
				IMPORT  stm32f103x_bsp_int_handler_TIM8_CC
				IMPORT  stm32f103x_bsp_int_handler_ADC3
				IMPORT  stm32f103x_bsp_int_handler_FSMC
				IMPORT  stm32f103x_bsp_int_handler_SDIO
				IMPORT  stm32f103x_bsp_int_handler_TIM5
				IMPORT  stm32f103x_bsp_int_handler_SPI3
				IMPORT  stm32f103x_bsp_int_handler_UART4
				IMPORT  stm32f103x_bsp_int_handler_UART5
				IMPORT  stm32f103x_bsp_int_handler_TIM6
				IMPORT  stm32f103x_bsp_int_handler_TIM7
				IMPORT  stm32f103x_bsp_int_handler_DMA2_CH1
				IMPORT  stm32f103x_bsp_int_handler_DMA2_CH2
				IMPORT  stm32f103x_bsp_int_handler_DMA2_CH3
				IMPORT  stm32f103x_bsp_int_handler_DMA2_CH4_5

; Vector Table Mapped to Address 0 at Reset
                AREA    RESET, DATA, READONLY
                EXPORT  __Vectors
                EXPORT  __Vectors_End
                EXPORT  __Vectors_Size

__Vectors       DCD     __initial_sp							     ; Top of Stack
                DCD     Reset_Handler								 ; Reset Handler
                DCD     stm32f103x_app_int_handler_NMI               ; NMI Handler
                DCD     stm32f103x_app_int_handler_HardFault		 ; Hard Fault Handler
                DCD     stm32f103x_app_int_handler_MemManage		 ; MPU Fault Handler
                DCD     stm32f103x_app_int_handler_BusFault			 ; Bus Fault Handler
                DCD     stm32f103x_app_int_handler_UsageFault        ; Usage Fault Handler
                DCD     0											 ; Reserved
                DCD     0										     ; Reserved
                DCD     0											 ; Reserved
                DCD     0											 ; Reserved
                DCD     stm32f103x_app_int_handler_SVC				 ; SVCall Handler
                DCD     stm32f103x_app_int_handler_DebugMon			 ; Debug Monitor Handler
                DCD     0											 ; Reserved
				DCD     OS_CPU_PendSVHandler						 ; 14, PendSV Handler                                          
				DCD     OS_CPU_SysTickHandler						 ; 15, uC/OS-II Tick ISR Handler

                ; External Interrupts
               DCD     stm32f103x_bsp_int_handler_WWDG                          ; 16, INTISR[  0]  Window Watchdog.                   
			   DCD     stm32f103x_bsp_int_handler_PVD                           ; 17, INTISR[  1]  PVD through EXTI Line Detection.    
			   DCD     stm32f103x_bsp_int_handler_TAMPER                        ; 18, INTISR[  2]  Tamper Interrupt.                   
			   DCD     stm32f103x_bsp_int_handler_RTC                           ; 19, INTISR[  3]  RTC Global Interrupt.               
			   DCD     stm32f103x_bsp_int_handler_FLASH                         ; 20, INTISR[  4]  FLASH Global Interrupt.             
			   DCD     stm32f103x_bsp_int_handler_RCC                           ; 21, INTISR[  5]  RCC Global Interrupt.               
			   DCD     stm32f103x_bsp_int_handler_EXTI0                         ; 22, INTISR[  6]  EXTI Line0 Interrupt.               
			   DCD     stm32f103x_bsp_int_handler_EXTI1                         ; 23, INTISR[  7]  EXTI Line1 Interrupt.               
			   DCD     stm32f103x_bsp_int_handler_EXTI2                         ; 24, INTISR[  8]  EXTI Line2 Interrupt.               
		   	   DCD     stm32f103x_bsp_int_handler_EXTI3                         ; 25, INTISR[  9]  EXTI Line3 Interrupt.               
			   DCD     stm32f103x_bsp_int_handler_EXTI4                         ; 26, INTISR[ 10]  EXTI Line4 Interrupt.               
			   DCD     stm32f103x_bsp_int_handler_DMA1_CH1                      ; 27, INTISR[ 11]  DMA Channel1 Global Interrupt.      
			   DCD     stm32f103x_bsp_int_handler_DMA1_CH2                      ; 28, INTISR[ 12]  DMA Channel2 Global Interrupt.      
			   DCD     stm32f103x_bsp_int_handler_DMA1_CH3                      ; 29, INTISR[ 13]  DMA Channel3 Global Interrupt.      
			   DCD     stm32f103x_bsp_int_handler_DMA1_CH4                      ; 30, INTISR[ 14]  DMA Channel4 Global Interrupt.      
			   DCD     stm32f103x_bsp_int_handler_DMA1_CH5                      ; 31, INTISR[ 15]  DMA Channel5 Global Interrupt.      

			   DCD     stm32f103x_bsp_int_handler_DMA1_CH6                      ; 32, INTISR[ 16]  DMA Channel6 Global Interrupt.      
			   DCD     stm32f103x_bsp_int_handler_DMA1_CH7                      ; 33, INTISR[ 17]  DMA Channel7 Global Interrupt.      
			   DCD     stm32f103x_bsp_int_handler_ADC1_2                        ; 34, INTISR[ 18]  ADC1 & ADC2 Global Interrupt.       
			   DCD     stm32f103x_bsp_int_handler_USB_HP_CAN_TX                 ; 35, INTISR[ 19]  USB High Prio / CAN TX  Interrupts. 
			   DCD     stm32f103x_bsp_int_handler_USB_LP_CAN_RX0                ; 36, INTISR[ 20]  USB Low  Prio / CAN RX0 Interrupts. 
			   DCD     stm32f103x_bsp_int_handler_CAN_RX1                       ; 37, INTISR[ 21]  CAN RX1 Interrupt.                  
			   DCD     stm32f103x_bsp_int_handler_CAN_SCE                       ; 38, INTISR[ 22]  CAN SCE Interrupt.                  
			   DCD     stm32f103x_bsp_int_handler_EXTI9_5                       ; 39, INTISR[ 23]  EXTI Line[9:5] Interrupt.           
			   DCD     stm32f103x_bsp_int_handler_TIM1_BRK                      ; 40, INTISR[ 24]  TIM1 Break  Interrupt.              
			   DCD     stm32f103x_bsp_int_handler_TIM1_UP                       ; 41, INTISR[ 25]  TIM1 Update Interrupt.              
			   DCD     stm32f103x_bsp_int_handler_TIM1_TRG_COM                  ; 42, INTISR[ 26]  TIM1 Trig & Commutation Interrupts. 
			   DCD     stm32f103x_bsp_int_handler_TIM1_CC                       ; 43, INTISR[ 27]  TIM1 Capture Compare Interrupt.     
			   DCD     stm32f103x_bsp_int_handler_TIM2                          ; 44, INTISR[ 28]  TIM2 Global Interrupt.              
			   DCD     stm32f103x_bsp_int_handler_TIM3                          ; 45, INTISR[ 29]  TIM3 Global Interrupt.              
			   DCD     stm32f103x_bsp_int_handler_TIM4                          ; 46, INTISR[ 30]  TIM4 Global Interrupt.              
			   DCD     stm32f103x_bsp_int_handler_I2C1_EV                       ; 47, INTISR[ 31]  I2C1 Event  Interrupt.              

			   DCD     stm32f103x_bsp_int_handler_I2C1_ER                       ; 48, INTISR[ 32]  I2C1 Error  Interrupt.              
			   DCD     stm32f103x_bsp_int_handler_I2C2_EV                       ; 49, INTISR[ 33]  I2C2 Event  Interrupt.              
			   DCD     stm32f103x_bsp_int_handler_I2C2_ER                       ; 50, INTISR[ 34]  I2C2 Error  Interrupt.             
			   DCD     stm32f103x_bsp_int_handler_SPI1                          ; 51, INTISR[ 35]  SPI1 Global Interrupt.              
			   DCD     stm32f103x_bsp_int_handler_SPI2                          ; 52, INTISR[ 36]  SPI2 Global Interrupt.              
			   DCD     stm32f103x_bsp_int_handler_USART1                        ; 53, INTISR[ 37]  USART1 Global Interrupt.            
			   DCD     stm32f103x_bsp_int_handler_USART2                        ; 54, INTISR[ 38]  USART2 Global Interrupt.            
			   DCD     stm32f103x_bsp_int_handler_USART3                        ; 55, INTISR[ 39]  USART3 Global Interrupt.            
			   DCD     stm32f103x_bsp_int_handler_EXTI15_10                     ; 56, INTISR[ 40]  EXTI Line [15:10] Interrupts.       
			   DCD     stm32f103x_bsp_int_handler_RTCAlarm                      ; 57, INTISR[ 41]  RTC Alarm EXT Line Interrupt.       
			   DCD     stm32f103x_bsp_int_handler_USBWakeUp                     ; 58, INTISR[ 42]  USB Wakeup from Suspend EXTI Int.   
			   DCD	   stm32f103x_bsp_int_handler_TIM8_BRK
			   DCD     stm32f103x_bsp_int_handler_TIM8_UP
			   DCD     stm32f103x_bsp_int_handler_TIM8_TRG_COM
			   DCD     stm32f103x_bsp_int_handler_TIM8_CC
			   DCD     stm32f103x_bsp_int_handler_ADC3
			   DCD     stm32f103x_bsp_int_handler_FSMC
			   DCD     stm32f103x_bsp_int_handler_SDIO
			   DCD     stm32f103x_bsp_int_handler_TIM5
			   DCD     stm32f103x_bsp_int_handler_SPI3
			   DCD     stm32f103x_bsp_int_handler_UART4
			   DCD     stm32f103x_bsp_int_handler_UART5
			   DCD     stm32f103x_bsp_int_handler_TIM6
			   DCD     stm32f103x_bsp_int_handler_TIM7
			   DCD     stm32f103x_bsp_int_handler_DMA2_CH1
			   DCD     stm32f103x_bsp_int_handler_DMA2_CH2
			   DCD     stm32f103x_bsp_int_handler_DMA2_CH3
			   DCD     stm32f103x_bsp_int_handler_DMA2_CH4_5
__Vectors_End

__Vectors_Size  EQU  __Vectors_End - __Vectors

                AREA    |.text|, CODE, READONLY
                
; Reset handler
Reset_Handler   PROC
                EXPORT  Reset_Handler             [WEAK]
                IMPORT  __main
                IMPORT  SystemInit
                LDR     R0, =SystemInit
                BLX     R0               
                LDR     R0, =__main
                BX      R0
                ENDP
                
; Dummy Exception Handlers (infinite loops which can be modified)

;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
                 IF      :DEF:__MICROLIB
                
                 EXPORT  __initial_sp
                 EXPORT  __heap_base
                 EXPORT  __heap_limit
                
                 ELSE
                
                 IMPORT  __use_two_region_memory
                 EXPORT  __user_initial_stackheap
                 
__user_initial_stackheap

                 LDR     R0, =  Heap_Mem
                 LDR     R1, =(Stack_Mem + Stack_Size)
                 LDR     R2, = (Heap_Mem +  Heap_Size)
                 LDR     R3, = Stack_Mem
                 BX      LR

                 ALIGN

                 ENDIF
				 ALIGN
                 END
				 

;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
